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this datasheet contains new product information. anachip corp. re serves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. rev. 1.0 dec 16, 2004 1/11 features peel? 16cv8 -25 cmos programmable electrically erasable logic device compatible with popular 16v8 devices - 16v8 socket and function compatible - programs with standard 16v8 jedec file - 20-pin dip, soic, tssop, and plcc cmos electrically erasable technology - superior factory testing - reprogrammable in plastic package - reduces retrofit and development costs application versatility - replaces random logic - super sets standard 20-pin plds (pals) multiple speed, power options - speeds range 25ns - power as low as 37ma @ 25mhz development / programmer support - third party software and programmers - anachip winplace development software - automatic programmer translation and jedec file translation software available for the most popular pal devices general description the peel tm 16cv8 is a programmable electrically erasable logic (peel) device providing an attractive alternative to ordinary plds. the peel tm 16cv8 offers the performance, flexibility, ease of design and production practicality needed by logic designers today. the peel tm 16cv8 is available in 20-pin dip, plcc, soic and tssop packages (see figure 1) with 25ns speed and power consumption as low as 37ma. ee-reprogrammability provides the convenience of instant reprogramming for development and reusable production inven- tory minimizing the impact of programming changes or errors. ee- reprogrammability also improves factory testability, thus assuring the highest quality possible. the peel tm 16cv8 architecture allows it to replace over standard 20- pin plds (pal, gal, epld etc.). see figure 2. anachip?s peel tm 16cv8 can be programmed with existing 16cv8 jedec file. some pro- grammers also allow the peel tm 16cv8 to be programmed directly from pld 16l8, 16r4, 16r6 and 16r8 jedec files. additional develop- ment and programming support for the peel tm 16cv8 is provided by popular third-party programmers and development software. anachip also offers free winplace development software. figure 1 - pin configuration figure 2 - block diagram not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 2/11 functional description the peel tm 16cv8 implements logic functions as sum-of- products expressions in a programmable-and/fixed-or logic array. user-defined functions are created by programmin g the connections of input signals into the array. user-configurable output structures in the form of macro- cells further increase logic flexibility. architecture overview the peel tm 16cv8 features ten dedicated input pins and eight i/o pins, which allow a total of up to 16 inputs and 8 outputs for creating logic functions. at the core of the device is a programmable electrically-eras- able and array which drives a fixed or array. with this structure the peel tm 16cv8 can implement up to 8 sum-of-products logic expres- sions. associated with each of the eight or functions is a macrocell which can be independently programmed to one of up to four different basic config- urations. the programmable macrocells allow each i/o to create sequential or combinatorial logic functions of active-high or active-low polarity, while providing two possible feedback paths into the array. three different device modes, simple, complex, and registered, sup- port various user configurations. in simple mode a macrocell can be configured for combinatorial function with the output buffer permanently enabled, or the output buffer can be disabled and the i/o pin used as a dedicated input. in complex mode a macrocell is configured for combi- 64 product terms: -56 product terms (arranged in 8 groups of 7) form sum-of-product functions for macrocell combinatorial or registered logic -8 product terms (arranged 1 per macrocell) add an additional product term for macrocell sum-of-products functions or i/o pin output enable control at each input-line/product-term intersection there is an eeprom mem- ory cell which determines whether or not there is a logical connection at that intersection. each product term is essentially a 32-input and gate. a product term which is connected to both the true and complement of an input signal will always be false and thus will not affect the or function that it drives. when all the connections on a product term are opened, that term will always be true. when programming the peel tm 16cv8, the device programmer first performs a bulk erase to remove the previous pattern. the erase cycle opens every logical connection in the ar ray. the device is configured to perform the user-defined function by programming selected connections in the and array. (note that peel tm device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function. natorial function with the output buffer enable controlled by a product term. in registered mode, a macrocell can be configured for registered operation with the register clock and output buffer enable controlled directly from pins, or can be configured for combinatorial function with the output buffer enable controlled by a product term. in most cases the device mode is set automatically by the development software, based on the features specified in the design. the three device modes support designs created explicitly for the peel tm 16cv8, as well as designs created originally for popular pld devices such as the 16r4, 16r8, and 16l8. table 1 shows the device mode used to emulate the various pl ds. design conversion into the 16cv8 is accommodated by jedec-to-jedec translators available from anachip, as well as several programmers which can read the origi- nal pld jedec file and automatically program the 16cv8 to perform the same function. and/or logic array the programmable and array of the peel tm 16cv8 is formed by input lines intersecting product terms. the input lines and product terms are used as follows: 32 input lines: -16 input lines carry the true and complement of the signals applied to the 8 dedicated input pins -16 additional lines carry the true and complement of 8 macrocell feedback signals or inputs from i/o pins or the clock/ oe pins table 1 : peel tm 16cv8 device compatibility pld architecture compatibility peel tm 16cv8 device mode 10h8 simple 10l8 simple 10p8 simple 12h6 simple 12l6 simple 12p6 simple 14h4 simple 14l4 simple 14p4 simple 16h2 simple 16hd8 simple 16l2 simple 16ld8 simple 16p2 simple 16h8 complex 16l8 complex 16p8 complex 16r4 registered 16r6 registered 16r8 registered 16rp4 registered not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 3/11 table 1 : peel tm 16cv8 device compatibility simple mode in simple mode, all eight product terms feed the or array which can pld architecture compatibility peel tm 16cv8 device mode generate a purely combinatorial function for the output pin. the pro- grammable output polarity selector allows active-high or active-low logic, 16rp6 registered 14rp8 registered programmable macrocell the macrocell provides complete control over the architecture of each output. the ability to configure each output independently permits users to tailor the configuration of the peel tm 16cv8 to the precise require- ments of their designs. macrocell architecture each macrocell consists of an or function, a d-type flip-flop, an output eliminating the need for external inverters. for output functions, the buffer can be permanently enabled. feedback into the array is available on all macrocell i/o pins, except for pins 15 and 16. figure 6 shows the logic array of the peel tm 16cv8 configured in simple mode. simple mode also provides the option of configuring an i/o pin as a ded- icated input. in this case, the output buffer is permanently disabled, and the i/o pin feedback is used to bring the input signal from the pin into the logic array. this option is available for all i/o pins except pins 15 and 16. figure 3 shows the possible simple mode macrocell configurations. polarity selector, and a programmable feedback path. four eeprom architecture bits ms0, ms1, op, and rc control the configuration of each macrocell. bits ms0 and ms1 are global, and select between sim- ple, complex, and registered mode for the whole device. bits op and rc are local for each macrocell; bit op controls the output polarity and bit rc selects between registered and combinatorial operation and also 1 simple mode active low output vcc 2 simple mode active high output vcc specifies the feedback path. table 2 shows the architecture bit settings for each possible configuration. equivalent circuits for the possible macroc ell configurations are illus- trated in figures 3, 4, and 5. when creating a peel tm device design, the desired macrocell configuration generally is specified explicitly in the design file. when the design is assembled or compiled, the macrocell configuration bits are defined in t he last lines of the jedec program- ming file. 3 simple mode i/o pin input figure 3 - macrocell configurations for simple mode of the peel tm 16cv8 (see figure 6 for logic array) table 2 : peel tm 16cv8 device mode/macrocell configuration bits not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 4/11 complex mode in complex mode, seven product terms feed the or array which can generate a purely combinatorial function for the output pin. the pro- grammable output polarity selector provides active-high or active-low logic, eliminating the need for external inverters. the output buffer is controlled by the eighth product term, allowing the macrocell to be con- figured for input, output, or bidirect ional functions. feedback into the array for input or bidirectional functions is available on all pins except 12 and 19. figure 4 shows the possible complex mode macrocell configura- tions. 1 registered mode active low registered output oe pin d q q clk pin 3 registered mode active low combinatorial output product term 2 registered mode active high registered output oe pin d q q clk pin 4 registered mode active high combinatorial output product term 1 complex mode active low output product term 2 complex mode active high output product term figure 5 - macrocell configurations for the registered mode of the peel tm 16cv8 (see figure 8 for logic array) figure 4 - macrocell configurations for the complex mode of the peel tm 16cv8 (see figure 7 for logic array) registered mode registered mode provides eight product terms to the or array for regis- tered functions. the programmable output polarity selector provides active-high or active-low logic, el iminating the need for external invert- ers. (note, however, that if register is selected, the peel tm 16cv8 reg- gisters power-up reset and so before the first clock arrives the output at the pin will be low if the user has selected active-high logic and high if the user has selected active-low logic. if combinatorial is selected, the output will be a function of the logic.) for registered functions, the output buffer enable is controlled directly from t he /oe control pin. feedback into the array comes from the macrocell register. in registered mode, input pins 1 and 11 are permanently allocated as clk and /oe, respec- tively. figure 8 shows the logic array of the peel tm 16cv8 configured in registered mode. registered mode also provides the option of configuring a macrocell for combinatorial operation, with seven product terms feeding the or func- tion. again the programmable output polarity selector provides active-high or active-low logic. the output buffer enable is controlled by the eighth product term, allowing the macrocell to be configured for input, output, or bidirectional functions. feedback into the array for input or bidirectional functions is available on all i/o pins. macrocell configurations for the registered mode of the peel tm 16cv8 design security the peel tm 16cv8 provides a special eeprom security bit that pre- vents unauthorized reading or copyin g of designs programmed into the device. the security bit is set by the pld programmer, either at the con- clusion of the programming cycle or as a separate step, after the device has been programmed. once the security bit has been set it is impossi- ble to verify (read) or program the peel tm until the entire device has first been erased with the bulk-erase function. signature word the signature word feature allows a 64-bit code to be programmed into the peel tm 16cv8. the code cannot be read back after the security bit has been set. the signature word can be used to identify the pattern programmed into the device or to record the design revision, etc. not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 5/11 1 i macro cell 2 i macro cell 19 i/o 18 i/o i 3 macro cell 17 i/o i 4 macro cell 16 i/o i 5 macro cell 15 i/o i 6 macro cell 14 i/o i 7 macro cell 13 i/o i 8 macro cell 12 i/o i 9 i 11 figure 6 - peel tm 16cv8 logic array - simple mode (see figure 3 for macrocell details) not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 6/11 not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 7/11 clk 1 i 2 macro cell macro cell 19 i/o 18 i/o i 3 macro cell 17 i/o i 4 macro cell 16 i/o i 5 macro cell 15 i/o i 6 macro cell 14 i/o i 7 macro cell 13 i/o i 8 macro cell 12 i/o i 9 11 oe figure 8 - peel tm 16cv8 logic array - registered mode (see figure 5 for macrocell details) not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 8/11 absolute maximum ratings this device has been designed and tested for the specified operating ranges. imp roper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may cause permanent damage. symbol parameter conditions rating unit v cc supply voltage relative to ground -0.5 to +6.0 v v o voltage applied to any pin 2 relative to ground 1 -0.5 to v cc +0.6 v i o output current per pin (i ol , i oh ) +25 ma t st storage temperature -65 to +150 o c t lt lead temperature soldering 10 seconds +300 o c operating range symbol parameter conditions min max unit v cc supply voltage commercial 4.75 5.25 v t a ambient temperature commercial 0 +70 o c t r clock rise time see note 3. 20 ns t f clock fall time see note 3. 20 ns t rvcc v cc rise time see note 3. 250 ms d.c. electrical characteristics over the operating range (unless otherwise specified) symbol parameter conditions min max unit v oh output high voltage ? ttl v cc =min, i oh =-4.0ma 2.4 v v ohc output high voltage ? cmos v cc =min, i oh =-10a v cc -0.3 v v ol output low voltage ? ttl v cc =min, i ol =16ma 0.5 v v olc output low voltage ? cmos v cc =min, i ol =10a 0.15 v v ih input high level 2.0 v cc +0.3 v v il input low voltage -0.3 0.8 v i il input, i/o leakage current low v cc =max, v in =gnd, i/o=high z -10 a i ih input, i/o leakage current high v cc =max, v in =gnd, i/o=high z 0(typical) 40 a i cc 10 v cc current, f=1mhz v in =0v or v cc , f=25mhz all outputs disabled 4 -25 37 ma c in 7 input capacitance 6 pf c out 7 output capacitance t a =25oc, v cc =5.0v @f=1mhz 12 pf not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 9/11 a. c. electrical characteristics over the operating range 8, 11 symbol parameter min max unit t pd input 5 to non-registered output 25 ns t oe input 5 to output enable 6 25 ns t od input 5 to output disable 6 25 ns t co1 clock to output 15 ns t co2 clock to comb. output delay via internal registered feedback 35 ns t cf clock to feedback 10 ns t sc input 5 or feedback setup to clock 20 ns t hc input 5 hold after clock 0 ns t cl, tch clock low time, clock high time 8 15 ns t cp min clock period ext (t sc + t co1 ) 35 ns f max1 internal feedback (1/t sc +t cf ) 11 28.5 mhz f max2 external feedback (1/t cp ) 11 28.5 mhz f max3 no feedback (1/t cl +t ch ) 11 33.3 mhz t aw asynchronous reset pulse width 25 ns t ap input 5 to asynchronous reset 25 ns t ar asynchronous reset recovery time 25 ns t reset power-on reset time for registers in clear state 5 s switching waveforms inputs, i/o, registered feedback, synchronous preset clock asynchronous reset registered outputs combinatorial outputs notes: 1. minimum dc input is -0.5v, however, inputs may undershoot to -2.0v for periods less than 20 ns. 2. v i and v o are not specified for program/verify operation. 3. test points for clock and vcc in t r and t f are referenced at the 10% and 90% levels. 4. i/o pins are 0v and v cc . 5. ?input? refers to an input pin signal. 6. t oe is measured from input transition to v ref 0.1v, t od is measured from input transi- tion to v oh -0.1v or v ol +0.1v; v ref =v l. 7. capacitances are tested on a sample basis. 8. test conditions assume: signal transition times of 3ns or less from the 10% and 90% points, timing reference levels of 1.5v (unless otherwise specified). 9. test one output at a time for a duration of less than 1 second. 10. i cc for a typical application: this parameter is tested with the device programmed as an 8-bit counter. 11. parameters are not 100% tested. specifications are based on initial characterization and are tested after any design process modification that might affect operational fre- quency. not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 10/11 ordering information part number speed temperature package peel tm 16cv8p-25 (l) 25ns c p20 peel tm 16cv8j-25 (l) 25ns c j20 peel tm 16cv8s-25 (l) 25ns c s20 peel tm 16cv8t-25 (l) 25ns c t20 part number peel tm 16cv8p-25x package p = plastic 300mil dip s = soic temperature range (blank) = commercial temperature 0 to 70 o c speed -25 = 25ns tpd lead free blank : normal l : lead free package j = plastic (j) leaded chip carrier (plcc) suffix device t = tssop not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 11/11 anachip corp. head office , anachip usa 2f, no. 24-2, industry e. rd. iv, sci ence-based 780 montague expressway, #201 industrial park, hsinchu, 300, taiwan san jose, ca 95131 tel: +886-3-5678234 tel: (408) 321-9600 fax: +886-3-5678368 fax: (408) 321-9696 email: sales_usa@anachip.com website: http://www.anachip.com ?2004 anachip corp. anachip reserves the right to make changes in specifications at any time and wit hout notice. the information furnished by anachip in this publication is believed to be accurate and reliabl e. however, there is no responsibility assumed by anachip for its use nor for any infringements of patents or other rights of third parties resultin g from its use. no license is granted und er any patents or patent rights of anachip. anachi p?s products are not authorized for use as cr itical components in life support devic es or systems. marks bearing ? or ? are registered trademar ks and trademarks of anachip corp. not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service

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